![]() ![]() Our focus on CL16 freed up time to test that new variable we mentioned earlier: infinity fabric overclocking. As these kinds of latencies are far more common at lower frequencies, we therefore opted to focus the majority of our testing at CL16, bumping up the voltage from 1.35V to 1.40V as we did so. Thanks to the testing we did with the same 4000MHz RAM kit in part one, we knew that our sticks could hit 4000MHz with tighter 16-17-17-34 timings without any instability. Meanwhile, the transcode test utilises the popular open source Handbrake application, and tests how quickly our test rig can transcode one of our Patreon video files into x264 and x265 (HEVC) formats using the Production Standard preset at quality setting RF 18. The rendering side is handled by Cinebench R20, an industry-wide CPU benchmark that mimics the creation of a 3D scene in professional 3D software suite Cinema 4D. As usual, we've tested two popular tasks, 3D scene rendering and video transcoding. Let's move onto the next tests, and then we can cover why we chose these particular configurations in more depth. Meanwhile, latency increased by around 7ns between our CL16 and CL19 results at 4000MHz, and otherwise slowly increased as we go down the chart - with a few exceptions. That means in the perfect RAM-bound scenario, we'd expect to see a maximum performance advantage of only around 60 to 70 per cent by nearly doubling our RAM frequency. This advantage was 58 per cent in terms of write speeds and 65 per cent for copy speeds. ![]() In total, our fastest result (3800MHz CL16 with a fabric clock of 1900MHz) boasted 73 per cent better read speeds than our slowest result (2133MHz CL16). You can see how, as memory frequencies ramp up, we get a corresponding increase in read, write and copy speeds. For each configuration, we listed the frequency (in MHz), the latency (normally CL16) and the fabric clock (which we'll get into later). This'll allow us to see the theoretical maximum performance boost we'd see in a task that is limited only by memory speed, setting a kind of upper bound on the sort of gains we'd see from faster RAM in other tasks like content creation or gaming.įor this, we used Aida64's cache and memory benchmark, which includes four RAM-specific tests measuring read speeds, write speeds and copy speeds, plus latency. You can join the discussion on AMD's Zen 3 Milan series processors using DDR4 memory on the OC3D Forums.Before we get into content creation, let's start with a synthetic benchmark that measures RAM speed specifically. With each new Zen architecture, AMD plans to eliminate more shortcomings within their designs, hoping to eliminate all of Intel's performance advantages over time to deliver "IPC (or better) parity across all workloads." ![]() AMD has already committed to utilising a "7nm+" manufacturing process to create their next-generation Ryzen and EPYC series CPUs, with Zen 3 aiming to remove for "asterisks" from the company's processor designs. 2020's Ryzen 4th Generation processors are likely to be the last AMD CPUs to use DDR4 memory. With Milan supporting DDR4 and the same SP3 socket as today's EPYC processors, it seems likely that AMD's Zen 3 desktop processors will also continue to utilise DDR4 memory. "DDR5 is a different design," and as such it will require a new CPU socket from AMD. In this interview, AMD's Forrest Norrod also confirmed that their Zen 3 "Milan" processors would support the SP3 server socket, which is the same as what's currently used for the company's EPYC and EPYC 2nd Generation processors, confirming that "Milan" will also support DDR4 memory. With Zen 2 "Rome" processors, AMD plans to up their DDR4 memory support from 2666MHz to an unknown higher speed, which AMD's Forrest Norrod stating that "you do get more than DDR4-2666" in a recent interview with Anandtech. Moving forward, AMD plans to continue to innovate within the CPU market, with plans to release "Zen 3" processors in mid-2020 with their "Milan" server parts. AMD's Zen 2 series of processors will soon be upon us, bringing with them higher core counts, heightened efficiency and increased IPC. ![]()
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